HARDWARE IMPLEMENTATION OF 'AES' DATA ENCRYPTION AND DECRYPTION ALGORITHM WITH A FIELD PROGRAMMABLE GATE ARRAY

Abstract

This research presents the design of an FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm. We live in an age where digital data, and its security, are of prime importance. Just as the complexity of networks and data transmission methods grows, so also the rise in incidence of digital crimes and the increase in complexities of network security attack methods. Given the rapid evolution of attack methods and toolkits, software-based solutions to secure the network infrastructure have become overburdened. Therefore, the use of hardware implementations for securing the network infrastructure has been considered. Field Programmable Gate Array (FPGA) devices have commonly been proposed for this purpose because they feature both the flexibility of software and the high performance of hardware. In this research, we implemented a complex encryption algorithm, the AES algorithm, on an FPGA and compared it with its software implementation. An optimizeable VISIC-VHDL code was written as a custom instruction to speed up the operation of the substitution phases of the data encryption algorithm. As a result of this approach, we have been able to save a considerable amount of time needed to perform a substitution task in each of the iteration phase of the encryption/decryption module, which is of course an improvement on previous implementations. The speed obtained after the simulation and testing of our design shows that, it is clearly a viable and worthwhile option to use reconfigurable hardware devices for the implementation of security algorithms, rather than using a slower software implementation that increases the burden on the main processor, thereby reducing its efficiency.